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ucc2882/-1 ucc3882/-1 03/99 features combined dac/voltage monitor and pwm with synchronous rectification functions 5-bit digital-to-analog (dac) converter 1% dac/reference combined accuracy compatible with 5v and 12v systems and 12v-only systems low offset current sense amplifier programmable oscillator frequency practical to 700khz foldback current limiting overvoltage and undervoltage fault windows 2 w totem pole outputs with programmable dead times to eliminate cross-conduction chip disable function average current mode synchronous controller with 5-bit dac block diagram udg-97047-1 description the ucc3882 combines high precision reference and voltage monitoring circuitry with average current mode pwm synchro- nous rectification controller circuitry to power high-end micropro- cessors with a minimum of external components. the ucc3882 converts 5v or 12v to an adjustable output ranging from 1.8vdc to 2.05vdc in 50mv steps and 2.1vdc to 3.5vdc in 100mv steps with 1% dc system accuracy. the dac output voltage is directly compatible with intels 5-bit vid code (table 1) which covers 1.3v to 2.05v in 50mv steps and 2.1v to 3.5v in 100mv steps. the accuracy of the dac/ref- erence combination is better than 1%. undervoltage lockout cir- cuitry assures the correct logic states at the outputs during power up and power down. the overvoltage and undervoltage comparators monitor the system output voltage and indicate when it rises above or falls below its designed value by more than 9%. a second overvoltage comparator digitally forces gatehi off and gatelo on when the system output voltage ex- ceeds its designed value by more than 17.5%. (continued)
2 ucc2882/-1 ucc3882/-1 gatelo n/c d1 d0 vdrvhi d2 d3 d4 gnd n/c pwrgd vdrvlo is+ vin cam cao isout vsns isC pgnd en vref command gatehi rt ct vfb comp 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 connection diagram dil-28, soic-28 (top view) n, dw or pw packages electrical characteristics: unless otherwise specified, vin = vdrvhi = vdrvlo = 12v, vsns = 3.5v, v d0 = v d1 = v d2 = v d3 = v d4 = 0v, r t = 13k, c t = 1.8nf, en = open, 0c < t a < 70c, t a =t j . parameter test conditions min typ max units undervoltage lockout vin uvlo turn-on threshold 10.5 10.8 v vin uvlo turn-off threshold 9.5 10 v uvlo threshold hysteresis 300 500 700 mv supply current l in en = 0v 7 12 ma for all of the parts, grounding the en pin disables the gatehi and gatelo outputs, shutting down the power supply. for the 2882 and 3882 only, programming a dac output voltage below 1.8v, or programming all of the vid pins high also disables the gatehi and gatelo out- puts. for the C1" option parts, the gatehi and gatelo outputs are switching, and the power supply output volt- age regulates at the programmed dac output voltage for all vid codes. the voltage and current amplifiers have 2.5mhz gain-bandwidth product to satisfy high performance sys- tem requirements. the internal current sense amplifier permits the use of a low value current sense resistor, minimizing power loss. the oscillator frequency is exter- nally programmed with r t and c t . the foldback circuit reduces the converter short circuit current limit to 50% of its nominal value when the converter is short-circuited, minimizing component stress and dissipation during ab- normal conditions. the gate drivers are low impedance totem pole output stages capable of driving large exter- nal mosfets. cross conduction is eliminated internally by programming the dead time between turn-off and turn on of the external high side and synchronous mosfets. this device is available in a 28-pin wide body surface mount package. the ucc2882 is specified for operation from C25c to +85c and the ucc3882 is specified for operation from 0c to 70c. description (continued) absolute maximum ratings vdrvhi, gatehi (note 1) . . . . . . . . . . . . . . . . . C0.3v to 20v vdrvlo, gatelo. . . . . . . . . . . . . . . . . . . . . . . . C0.3v to 15v all other pins referenced to gnd . . . . . . . . . . . . . C0.3v to 5.3v vin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15v storage temperature . . . . . . . . . . . . . . . . . . . C65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . C55c to +150c lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . +300c currents are positive into, negative out of the specified terminal. consult packaging section of databook for thermal limitations and considerations of packages. note 1: 20v at no load. derate to 18.5v when used with capaci- tive loads of greater than 1000pf in series with less than 20 w .
3 ucc2882/-1 ucc3882/-1 electrical characteristics: unless otherwise specified, vin = vdrvhi = vdrvlo = 12v, vsns = 3.5v, v d0 = v d1 = v d2 = v d3 = v d4 = 0v, r t = 13k, c t = 1.8nf, en = open, 0c < t a < 70c, t a =t j . parameter test conditions min typ max units dac/reference command voltage accuracy 10.8v < vin < 13.2v, i ref = 0ma (note 1) C1 1 % d0-d4 voltage high dx pin floating 5 5.2 v d0-d4 input bias current dx pin tied to gnd C120 C70 C20 m a ovp comparator trip point % over command voltage (note 2) 10 17 25 % hysteresis 20 mv ov comparator trip point % over command voltage (note 2) 5 9 12 % hysteresis 20 mv pwrgd on resistance 470 w uv comparator trip point % over command voltage (note 2) C12 C9 C5 % hysteresis 20 mv enable pin pull up current v en = 2.5v C80 C50 C20 m a voltage error amplifier input offset voltage v cm = 3v C10 0 10 mv input bias current v cm = 3v C0.5 0.5 m a open loop gain 2.05v < v comp < 3.05v 90 db power supply rejection ratio 10.8v < vin < 15v 85 db output sourcing current v vfb = 2v, v command = v comp = 2.5v C1.6 C0.8 ma output sinking current v vfb = 3v, v command = v comp = 2.5v 1 ma current sense amplifier gain 15 16 17 v/v common mode rejection ratio 0v < v cm < 4.5v 60 db power supply rejection ratio 10.8v < vin < 15v 80 db output sourcing current v is C = 2v, v isout = v is + = 2.5v C4 C3 ma output sinking current v isC = 3v, v isout = v is+ = 2.5v 3 4 ma current amplifier input offset voltage v cm = 3v 1 mv input bias current v cm = 3v C0.1 m a open loop gain 1v < v cao < 2.5v 90 db output voltage high 3v power supply rejection ratio 10.8v < vin < 15v 80 db output sourcing current v cam = 2v, v cao = v comp = 2.5v C7 ma output sinking current v cam = 3v, v cao = v comp = 2.5v 17 ma oscillator initial accuracy t a = 25c 324 360 396 khz 0c < t a < 70c 300 360 420 khz valley to peak voltage 1.67 v frequency change with voltage 10.8v < vin < 15v 1 % output section (gatehi and gatelo) output low voltage i gate = C100ma 0.2 v output high voltage i gate = 100ma 11.8 v rise time c gate = 3.3nf, r series = 10 w 20 80 ns fall time c gate = 3.3nf, r series = 10 w 15 80 ns
4 ucc2882/-1 ucc3882/-1 cam: this pin is the inverting input to the current ampli- fier. the average load current feedback from the isout pin is applied through a resistor to this pin. the current loop compensation network is also connected to this pin (see cao below). cao: this pin is the current amplifier output. the current loop compensation network is connected between this pin and the cam pin. the voltage on this pin is the input to the pwm comparator and regulates the output voltage of the system. the voltage at this output ranges from be- low 0.5v (forcing 0% duty cycle) to above 2.5v forcing maximum duty cycle. a 3v clamp circuit prevents the cao voltage from rising excessively past the oscillator peak voltage, for excellent transient response. comp: this pin is the voltage error amplifier output volt- age. the system voltage compensation network is ap- plied between comp and vfb. a 1.37v clamp above command is used to force the power supply into cur- rent limit mode when the output is short circuited. see the applications section for programming current limit. command: this pin is the output of the 5-bit digi- tal-to-analog (dac) converter and is the non-inverting in- put of the voltage error amplifier. the voltage on this pin sets the switching regulator output voltage. the com- mand voltage is set by the dac input pins d0-d4, ac- cording to table 1. the command source impedance is typically 1.2k w and must therefore drive only high imped- ance inputs if accuracy is to be maintained. bypass command with a 0.01 m f, low esr, low esl capacitor for best circuit noise immunity. ct: this pin is used with rt to program the internal pwm oscillator frequency. use a high quality capacitor for best oscillator accuracy. see the applications section for programming the oscillator. d0-d4: these are the digital input control codes for the dac (see table 1). the dac is comprised of two ranges set by d4 and with d0 representing the least significant bit (lsb) and d3, the most significant bit (msb). a bit is set low by being connected to gnd; a bit is set high by floating it, or connecting it to a 5v source. each control pin is pulled up to approximately 5v by an internal pull up. en: this input is used to disable the gatehi and gatelo outputs, resulting in disabling the power supply. pulling en to gnd causes the gatehi and gatelo outputs to be held low, while floating the pin or pulling it up to 5v ensures normal operation. en is pulled up to 5v internally. gatehi: this output provides a low impedance totem pole driver to drive the high-side external mosfet. a se- ries resistor between this pin and the gate of the external mosfet is recommended to prevent gate drive ringing and overshoot. good layout techniques should be used to prevent gatehi from ringing more than 0.3v below pgnd. the vdrvhi pin provides the power for the gatehi pin. gatehi is disabled during uvlo and overvoltage conditions. for the 2882/3882 only, gatehi is also disabled when the command voltage is pro- grammed between 1.3 and 1.75v, or where the d0-d4 pins are all logic high levels, indicating no processor present. pin descriptions electrical characteristics: unless otherwise specified, vin = vdrvhi = vdrvlo = 12v, vsns = 3.5v, v d0 = v d1 = v d2 = v d3 = v d4 = 0v, r t = 13k, c t = 1.8nf, en = open, 0c < t a < 70c, t a =t j . parameter test conditions min typ max units turn on delay gatehi turn off to gatelo turn on 150 ns gatelo turn off to gatehi turn on 135 ns foldback current limit clamp level v command = v sns 1.37 v v fb = v command C 100mv (note 3) v sns = 0 0.71 v v fb = v command C 100mv (note 3) system short circuit current limit v command = 2.3v 14.4 17 22 a v fb = 0v (note 4) note 1: this test measures the combined errors of the command voltage and the voltage amplifier offset voltage. applies to all dac codes from 1.8v to 3.5v. note 2: this percentage is measured with respect to the ideal command voltage programmed by the d0 - d4 pins. note 3: this voltage is measured with respect to the command voltage. note 4: the calculation of this parameter assumes an offchip sense resistor value of 0.005 w . this test encompasses all sources of error from the ic.
5 ucc2882/-1 ucc3882/-1 gatelo: this output provides a low impedance totem pole driver to drive the low-side synchronous external mosfet. a series resistor between this pin and the gate of the external mosfet is recommended to prevent gate drive ringing and overshoot. good layout techniques should be used to prevent gatelo from ringing more than 0.3v below pgnd. the vdrvlo pin provides the power for gatelo. gatelo is disabled during uvlo conditions. for the 2882/3882 only, gatelo is also dis- abled when the command voltage is programmed be- tween 1.3 and 1.75v, or where the d0-d4 pins are all logic high levels, indicating no processor present. gnd: ground reference for the device. all voltages, with the exception of the gate voltages, are measured with respect to gnd. bypass capacitors on vin, vref, vsns and command should be connected directly to the ground plane near gnd. is-: this pin is the inverting input to the current sense amplifier and is connected to the low side of the average current sense resistor. is+: this pin is the non-inverting input to the current sense amplifier and is connected to the high side of the average current sense resistor. isout: this pin is the output of the current sense ampli- fier. the voltage on this pin is equal to the voltage across the sense resistor multiplied by 16 and biased up by the command voltage. this voltage is used for average current mode control and for current limiting. pgnd: this pin provides a dedicated ground for the out- put gate drivers. the gnd and pgnd pins should be connected externally using a short pc board trace or plane. decouple vdrvhi and vdrvlo to pgnd with low esr capacitor of at least 0.1 m f. pwrgd: this pin is an open drain output which is driven low to reset the microprocessor when vsns rises above or falls below its nominal value by 9%. the on resistance of the open-drain switch will be no higher than 470 w . this output should be pulled up to a logic level voltage and should be programmed to sink 1ma or less. rt: this pin is used with ct to program the internal pwm oscillator frequency. it is also used to program the delay times between the external mosfet turn on and turn off periods, which eliminates cross conduction in those mosfets. see the applications section for pro- gramming the oscillator and for controlling cross conduc- tion. vdrvhi: this pin supplies power to the high side output driver, gatehi. connect vdrvhi to an 18v or lower source for power supplies converting 12vdc to lower voltages, and to a 12v source for systems for power sup- plies converting 5vdc. this pin should be bypassed di- rectly to pgnd using a low esr capacitor. vdrvlo: this pin supplies power to the low side output driver, gatelo. vdrvlo is typically connected to a 12v source, but may be connected to a 5v source for driving logic level mosfets. this pin should be bypassed di- rectly to pgnd using a low esr capacitor. vin: this pin supplies power to the chip. connect vin to a stable voltage source that is at least 10.8v above gnd. the gatehi, gatelo and pwrgd outputs will be held low until vcc exceeds the upper undervoltage lockout threshold. this pin should be bypassed directly to gnd. vfb: this pin is the inverting input to the error amplifier. this input is connected to comp through a feedback network and to the power supply output through a resis- tor or a divider network. vref: this pin provides an accurate 5v reference and is internally short circuit current limited. vref powers the d/a converter and also provides a threshold voltage for the uvlo comparator. for best reference stability, by- pass vref directly to gnd with a low esr, low esl ca- pacitor of at least 0.01 m f. vsns: this pin is connected to the system output volt- age through a low pass r-c filter. when the voltage on vsns rises above or falls below the command voltage by 9%, the pwrgd output is driven low to reset the mi- croprocessor. when the voltage on vsns rises above the command voltage by 17.5%, the ovp comparator disables the gatehi output and enables the gatelo output, forcing 0% duty cycle on the power supply. this pin is also used by the foldback current limiting circuitry to indicate when the output voltage has been short cir- cuited. vsns should be decoupled very closely to the ic with a capacitor to gnd. the ov and uv comparators hysteresis is typically 20mv, requiring good layout and fil- tering techniques to insure that noise and ground-bounce do not inadvertently trip the ov and uv comparators. it is recommended that an r-c filter set to approximately fs/10 be used to filter noise from the system output, where fs is the oscillator frequency. pin descriptions (continued)
6 ucc2882/-1 ucc3882/-1 this ic is intended to be used in a high performance power supply to power the pentium ? ii or a similar pro- cessor. figure 1 shows a typical power supply application circuit which converts +5v to lower voltages required by the pentium ? ii processor. synchronous switching delay time figure 2 shows that the fundamental difference between a buck and a synchronous buck regulator is the use of a mosfet rather than a schottky diode as the low side or free-wheeling switch. in order to maintain safe and efficient operation of a syn- chronous buck regulator, both mosfets, q1 and q2, should never be turned on at the same time. having both mosfets on at the same time results in cross conduc- tion, which can result in excessively high power dissipa- tion in one or both mosfets. the ucc3882 has a built in delay between the turn off of one mosfet and the turn on of the other mosfet. this delay is a controlled delay between the gatehi and gatelo drive outputs and is programmable by the selection of the resistor r t . controlling the delay between the gate drive outputs is only part of the solution. the power supply designer must also understand intrinsic delays involving mosfet turn on, turn off, rise and fall times in order to insure that there is no cross conduction. it is recommended that a value between 10k w and 15k w be used for r t , which minimizes the delay and can result in the highest efficiency operation. a higher value of r t will result in a larger delay between the mosfet gate transitions. r t should be between 10k w minimum and 50k w maximum. programming the oscillator the first step in programming the oscillator is choosing the value of r t as described above. the second step is to program the frequency according to the curves shown in figure 3, by choosing the appropriate capacitor value. for convenience, values are shown in table 1 for nominal frequencies from 100khz to 700khz using standards re- sistors and capacitor values. application information digital command command gatehi/gatelo digital command command gatehi/gatelo d4 d3 d2 d1 d0 voltage status d4 d3 d2 d1 d0 voltage status 01111 1.300 note 1 11111 2.000 note 1 01110 1.350 note 1 11110 2.100 enabled 01101 1.400 note 1 11101 2.200 enabled 01100 1.450 note 1 11100 2.300 enabled 01011 1.500 note 1 11011 2.400 enabled 01010 1.550 note 1 11010 2.500 enabled 01001 1.600 note 1 11001 2.600 enabled 01000 1.650 note 1 11000 2.700 enabled 00111 1.700 note 1 10111 2.800 enabled 00110 1.750 note 1 10110 2.900 enabled 00101 1.800 enabled 10101 3.000 enabled 00100 1.850 enabled 10100 3.100 enabled 00011 1.900 enabled 10011 3.200 enabled 00010 1.950 enabled 10010 3.300 enabled 00001 2.000 enabled 10001 3.400 enabled 00000 2.050 enabled 10000 3.500 enabled table 1. programming the command voltage for the ucc3882 the 5-bit digital-to-analog converter (dac) is pro- grammed according to table 1.the command voltage is always active as long as the ucc3882 vin pin is above the undervoltage lockout voltage. for the 2882/3882 only, the output gate drives gatehi and gatelo are disabled at certain dac codes, as shown in table 1. disabling the gate drives disables the power supply. for the 2882 -1 and 3882 -1, the gatehi and gatelo drives are enabled for all dac codes. for a given code, the power supply output regulates at the cor- responding command voltage. dac information
7 ucc2882/-1 ucc3882/-1 figure 1. application circuit - pentium ? ii power supply. udg-97048-1 frequency r t c t (khz) (k w ) (pf) 100 14.7 5600 200 11.0 3900 300 10.5 2700 400 11.3 1800 500 12.7 1200 600 10.7 1200 700 11.0 1000 table 2. programming standard frequencies an excessively long delay time between gate drive sig- nals, or a delay time that is too small, will result in a inef- ficient power supply design. the third step in programming the oscillator is to observe the actual circuit waveforms to insure that the delay is optimal. the de- signer should vary r t and c t accordingly to adjust the delay time and to program the proper oscillator fre- quency. using an external schottky diode in parallel with the low side mosfet the purpose of using a synchronous buck regulator is to substitute a low voltage drop mosfet in place of a schottky diode as the low side switch. an external schottky diode may still be required however, in order to reduce the losses due to the reverse recovery of the low-side mosfet body diode. figure 4 illustrates the ef- fects on power losses due to the non-ideal nature of a typical mosfet body diode. i rm is the peak recovery current of the body diode of q2 and i lout is the current of the output inductor. using a parallel schottky diode can reduce these losses and increase circuit efficiency. the size of the diode should be increased as a function of load current, input voltage, and operating frequency. the diode should be as close to the lower mosfet, q2, as possible, to reduce stray inductance. application information (continued)
8 ucc2882/-1 ucc3882/-1 choosing r sense to set the current limit r sense is chosen to limit the maximum (short circuit) current of the power supply. the short circuit current equation for the ucc3882 is: isc = 1.37v rsense ? 16 and therefore, the value of the sense resistor, for a cho- sen short circuit current is: rsense = 1.37v isc ? 16 the short circuit current limit does vary slightly as a func- tion of the switching regulators output inductor value and operating frequency because a high value of ripple cur- rent will reduce the average short circuit current limit. figure 5 shows the variation in isc given common values for the ucc3882. the ucc3882 is nominally configured so that a 0.005m w resistor will set the current limit to ap- proximately 17a. the ucc3882 incorporates short circuit current foldback, as shown in figure 6. when the output of the power sup- ply is short circuited, the output voltage falls. when the output voltage reaches 1/2 of its nominal voltage (com- mand/2) then the output current is reduced. this feature reduces the amount of current in the mosfets and ca- pacitors, and insures high reliability. choosing vdrvlo, vdrvhi and vin the ucc3882 requires a nominal 12v input supplied at vin. vdrvlo and vdrvhi can be set to any voltage less than 18.5v, and may be set individually. a power supply deriving its power from +5v should use +12v at the vdrvhi pin, but may use either +5v or +12v de- pending on the drive requirements of the synchronous low-side mosfet. a power supply deriving its power from +12v should use +18v at vdrvhi in order to pro- vide adequate voltage (6v) gate drive to the high-side mosfet. vin must be less than +15v. input capacitors the input capacitors are chosen primarily based on their switching frequency rms current handling capability and their voltage rating. the input capacitors must handle vir- tually all of the rms current at the switching frequency, even if the circuit does not have an input inductor. the switching current in the input capacitors appears as shown in figure 7. aluminum or tantalum capacitors can be used. the amount of rms current in an electrolytic capacitor has a strong impact on the reliability and lifetime of the capaci- tor. other factors which affect the life of an input capaci- tor are internal heat rise, external airflow, the amount of time that the circuit operates at maximum current and the operating voltage. the curves in figure 8 show the rms current handled by the total input capacitance in typical vrm circuits powered from 5v or from 12v. application information 0 100 200 300 400 500 600 700 800 10 15 20 25 rt [kw] frequency [khz] 1.0nf 1.2nf 1.8nf 2.2n 2.7nf 3.9nf 5.6nf figure 3. programming ucc3882 oscillator frequency. figure 2. buck vs. synchronous buck regulator. udg-97049
9 ucc2882/-1 ucc3882/-1 4 4.5 5 5.5 6 6.5 13 14 15 16 17 18 19 20 short circuit current (a) rsense (mw) 200khz, 1.5mh 400khz, 3mh 200khz, 3mh 300khz, 1.5mh 400khz, 1.5mh { figure 5. short circuit current limit vs. rsense for various frequency and inductor values. 0 20 40 60 80 100 0 20406080100 % short circuit current % nominal vout figure 6. short circuit foldback reduces stress on circuit components by reducing short circuit current. figure 7. input capacitors current waveform. udg-96216 figure 4. effects of reverse recovery in a synchronous rectifier. application information (continued) udg-97051 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 10 11 12 13 14 15 16 17 18 19 20 load current (a) rms current for input caps [arms] . vin 5v, vout 1.8v vin 5v, vout 2.8v vin12v,vout2.8v vin12v,vout1.8v choose the type and number of input capacitors based on these curves by choosing the input voltage and nominal output voltage. example: for a 5v input, 1.8v output power supply with a load of 15 amperes, the input capacitors should be chosen for 7.5 amperes rms current. figure 8. load current vs rms current for input capacitors - pentium ? ii family.
10 ucc2882/-1 ucc3882/-1 demonstration kit design and performance a demonstration circuit was built based on the ucc3882 and utilizing an intel vrm 8.1 form factor connector. the schematic is shown in figure 9 and the bill of materials in table 3. the circuit is configured for the following oper- ating parameters: switching frequency = 225khz rated output current = 15a short circuit current = 17a nominal output voltage: 1.8v to 2.8v configured by vid code airflow: 100 lfm temperature: 0 to 60c regulation: per intel vrm 8.1 dc-dc converter design guidelines figures 12 - 14 show the performance of the circuit. application information (continued) ref description package u1 unitrode ucc3882 dac/pwm soic-28 wide c01 sanyo 6mv1500gx, 1500 m f, 6.3v, aluminum electrolytic 10x20mm radial can c02 sanyo 6mv1500gx, 1500 m f, 6.3v, aluminum electrolytic 10x20mm radial can c03 sanyo 6mv1500gx, 1500 m f, 6.3v, aluminum electrolytic 10x20mm radial can c04 sprague/vishay 595d475x0016a2b, 4.7uf 16v tantalum sprague size a c05 sanyo 6mv1500gx, 1500 m f, 6.3v, aluminum electrolytic 10x20mm radial can c06 sanyo 6mv1500gx, 1500 m f, 6.3v, aluminum electrolytic 10x20mm radial can c07 sanyo 6mv1500gx, 1500 m f, 6.3v, aluminum electrolytic 10x20mm radial can c08 sanyo 6mv1500gx, 1500 m f, 6.3v, aluminum electrolytic 10x20mm radial can c09 sanyo 6mv1500gx, 1500 m f, 6.3v, aluminum electrolytic 10x20mm radial can c10 0.10 m f ceramic 1206 smd c11 0.10 m f ceramic 1206 smd c12 0.01 m f ceramic 0603 smd c13 0.01 m f ceramic 0603 smd c14 0.01 m f ceramic 0603 smd c15 0.10 m f ceramic 1206 smd c17 68pf npo ceramic 0603 smd c18 1000pf ceramic 0603 smd c19 220pf npo ceramic 0603 smd c20 sanyo 6mv1500gx, 1500 m f, 6.3v, aluminum electrolytic 10x20mm radial can ct 3900pf ceramic 0603 smd j1 amp 532956-7 40 pin connector 40 pin l1 toroid t51-52c, 5 turns #16awg, 1.6 m h toroid q1 international rectifier irl3103, 30v, 56a to-220ab, layed down q2 international rectifier irl3103d1, 30v, 56a to-220ab, layed down r01 5m w , pcb resistor copper trace r02 10k w , 5%, 1/16 watt 0603 smd r03 5.62k w , 1%, 1/16 watt 0603 smd r05 365k w , 1%, 1/16 watt 0603 smd r06 100k w , 5%, 1/16 watt 0603 smd r07 5.6k w , 5%, 1/16 watt 0603 smd r08 10k w , 5%, 1/16 watt 0603 smd r09 3.3 w, 5%, 1/16 watt 0603 smd r10 3.3 w , 5%, 1/16 watt 0603 smd table 3. bill of materials.
11 ucc2882/-1 ucc3882/-1 figure 9. reference design - ucc3882 5-bit synchronous rectifier pwm controller for the intel pentium ? ii processor. application information (continued) udg-97140
12 ucc2882/-1 ucc3882/-1 application information (continued) figure 10. demo board. figure 11a. comp silkscreen. figure 11b. comp side. figure 11c. gnd layer. figure 11d. pwr layer. figure 11e. solder side. figure 11f. drill drawing.
13 ucc2882/-1 ucc3882/-1 unitrode corporation 7 continental blvd. ? merrimack, nh 03054 tel. (603) 424-2410 ? fax (603) 424-3460 application information (cont.) figure 12. transient response to 15.2a step load channel 2 scale is 50mv/a. 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 0.0 5.0 10.0 15.0 dc load current (a) efficieny (%) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 power dissipation (w) power dissipation efficiency figure 13. ucc3882 demo kit efficiency. -5.00% -3.00% -1.00% 1.00% 3.00% 5.00% 0 2 4 6 8 10 12 14 16 load current (a) voltage regulation figure 14. load regulation. pentium ? ii is a registered trademark of intel corporation.
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